A process for the formation of metal salicide regions and metal salicide exclusion regions in an integrated circuit (IC) that requires a minimum number of steps and is compatible with standard MOS processing techniques. In the process, an IC structure is first provided. The IC structure includes a plurality...http://www.google.sh/patents/US6329287?utm_source=gb-gplus-sharePatent US6329287 - Process for manufacturing an integrated circuit structure with metal salicide regions and metal salicide exclusion regions
