(12) United States Patent ao) Patent No.: us 6,329,287 Bi
Gadepally (45) Date of Patent: Dec. 11,2001
(54) PROCESS FOR MANUFACTURING AN
INTEGRATED CIRCUIT STRUCTURE WITH
METAL SALICIDE REGIONS AND METAL
SALICIDE EXCLUSION REGIONS
(75) Inventor: Kamesh V. Gadepally, San Jose, CA (US)
(73) Assignee: National Semiconductor Corporation,
Santa Clara, CA (US)
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.
(21) Appl. No.: 09/430,348
(22) Filed: Oct. 29, 1999
(51) Int. C I. H01L 21/44
(52) U.S. CI 438/674; 438/634; 438/649;
438/682; 438/683; 438/684; 257/757; 257/768;
257/769
(58) Field of Search 458/674, 682,
458/683, 684, 533, 558, 584, 586, 630, 649, 651, 655, 664, 249, 301, 342, 364, 542; 257/384, 757, 768, 764
(56) References Cited
U.S. PATENT DOCUMENTS
5,911,114 * 6/1999 Naem 438/684
5,970,370 * 12/1998 Besser et al 438/586
6,089,659 * 11/1998 Kepler et al 438/249
6,136,705 * 10/1998 Blair 438/682
OTHER PUBLICATIONS
S. Wolf, Silicon Processing for the VLSI Era, vol. I, pp. 388-399 (Lattice Press, 1986).
* cited by examiner
Primary Examiner—David Nelms
Assistant Examiner—Renee R. Berry
(74) Attorney, Agent, or Firm—Girard & Equitz LLP
(57) ABSTRACT
A process for the formation of metal salicide regions and metal salicide exclusion regions in an integrated circuit (IC) that requires a minimum number of steps and is compatible with standard MOS processing techniques. In the process, an IC structure is first provided. The IC structure includes a plurality of MOS transistor structures with exposed silicon surfaces, such as source regions, drain regions and polysilicon gates. A metal layer (e.g., cobalt, titanium, tantalum, nickel or molybdenum) is then deposited over the IC structure, followed by the formation of a photoresist masking layer on those MOS transistor structures where metal salicide regions are to be formed. The metal layer from those MOS transistor structures where metal salicide exclusion regions are to be formed is then removed, followed by stripping of the photoresist masking layer from those MOS transistor structures where metal salicide regions are to be formed. Metal in the metal layer that is in direct contact with silicon in the exposed silicon surfaces is subsequently reacted to form metal salicide regions.
7 Claims, 3 Drawing Sheets
